`timescale 1ns/1ns
module ALU_tb (
    
);

    reg [15:0] a,b;
    reg [3:0] ALUC;
    wire [15:0] ALU_out;

    initial begin
        a = {16{1'bx}};
        b = {16{1'bx}};
        ALUC = 4'bxxxx;

        #2
        a = 16'd220;
        b = 16'd100;
        ALUC[2:0] = 3'b000;
        ALUC[3] = 0;
        #2
        ALUC[3] = 1;
        #2
        forever begin
            #2 ALUC[2:0] = ALUC[2:0] + 1;
        end
    end

    ALU u_ALU(
    	.a       (a       ),
        .b       (b       ),
        .ALUC    (ALUC    ),
        .ALU_out (ALU_out )
    );
    
endmodule